1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device that has a plurality of clock domains that operate at different frequencies, and to a delay fault testing method thereof.
2. Description of Related Art
Conventionally, a large number of flip-flops are configured in a large-scale integrated circuit (LSI). For the purpose of fault diagnosis of such an LSI, a scan chain that is configured as scan flip-flops that have flip-flops inside the circuit in a chain path may be employed.
In recent years, accompanying the speeding up of the target circuits, a test for a delay fault (delay fault test) is also being employed. The delay fault test is adapted to determine whether or not data transition is possible within a predetermined delay time, for combinational circuit sections between flip-flops of a scan-designed circuit.
In the delay fault test, first, a scan chain is utilized to set required values for the flip-flops. Next, two clock signals are applied with frequencies desired for the test, at high speed. Thereby, a change in a value generated in a flip-flop at a former stage (hereafter, referred to as “pre-stage flip-flop”) with the initial clock pulse (launch pulse) is provided to a logic, and the output of the logic is captured by a flip-flop at a latter stage (hereafter, referred to as “post-stage flip-flop”) with the second clock pulse (capture pulse). By retrieving the output of the post-stage flip-flop via a scan chain, a delay fault of the logic at the test frequency between the pre-stage flip-flop and the post-stage flip-flop can be detected.
Further, in recent years, drive frequencies of elements inside LSIs have become extremely high. For example, in some cases a high speed clock having a frequency of 500 MHz is used. With respect to delay fault tests also, a test using a high speed clock is required in order to support such high speed operation. In this case, if it is attempted to supply a launch and a capture pulse (hereunder, also referred to as “test clock”) from a tester outside of the LSI, measurement of the delay fault test is difficult due to waveform distortion. Therefore, a method may be considered in which the test clock is generated by using output of a PLL circuit that is configured in the LSI.
Furthermore, inside an LSI, elements driving at a high speed and elements driving at a low speed are sometimes provided in a mixed manner. Even in this case, it is possible to perform a delay fault test with respect to each element group by supplying a high speed test clock to the elements driving at a high speed and supplying a low speed test clock to the elements driving at a low speed.
However, there are cases in which a logic that is the test object is located between an element group driving at a high speed and an element group driving at a low speed. That is, there are cases where a logic exists which is supplied with the output of an element group driving at a high speed, and whose output is output to an element group driving at a low speed.
Regarding this kind of logic, the pre-stage flip-flop belongs to an element group driving at a high speed and the post-stage flip-flop belongs to an element group driving at a low speed. In order to detect a delay fault in this kind of logic, it is necessary that a launch pulse for inputting a value into the logic and a capture pulse for capturing an output of the logic are high speed clocks. That is, it is necessary to supply a high speed clock to the post-stage flip-flop also, and this means that a high speed clock is supplied to the element group driving at a low speed. Operation according to a high speed clock is not guaranteed for an element group driving at a low speed, and in some cases errors occur due to timing violations when an element group driving at a low speed is operated with a high speed clock. In this case, since a detection result for a delay fault is obtained via a scan chain of the element group driving at a low speed, there is a possibility that the detection result for the delay fault will be an error.
In this connection, Japanese Patent Application Laid Open Publication No. 2007-327838 discloses a method that carries out a delay fault test using a high-speed test clock for elements driving at a high speed, and a low-speed test clock for elements driving at a low speed. However, according to the method disclosed in Japanese Patent Application Laid Open Publication No. 2007-327838, the circuitry is complicated because a high-speed test clock and a low-speed test clock are respectively supplied to the necessary elements.